英语缩略词“HSIC”经常作为“High Speed Integrated Circuit”的缩写来使用,中文表示:“高速集成电路”。本文将详细介绍英语缩写词HSIC所代表英文单词,其对应的中文拼音、详细解释以及在英语中的流行度。此外,还有关于缩略词HSIC的分类、应用领域及相关应用示例等。
以上为High Speed Integrated Circuit的英文缩略词HSIC的中文解释,以及该英文缩写在英语的流行度、分类和应用领域方面的信息。
VHDL ( Very High Speed Integrated Circuit(HSIC) Hardware Description Language ) is widely appped in electronic design fields today.
VHDL(超高速集成电路(HSIC)硬件描述语言)在电子设计领域中已得到了广泛用。
Introduces the development of very high speed integrated circuit hardware description language ( VHDL ), and presents the design mathod of system on chip on the basis of VHDL and complex programmable logic device ( CPLD ).
介绍了超高速集成电路(HSIC)硬件描述语言(VHDL)的发展历程,并且论述了利用VHDL。在复杂可编程逻辑器件(CPLD)上进行系统芯片(SOC)设计的方法。
Meanwhile, on base of this principle, adopts Verilog HDL to design high speed integrated circuit for equal observations of frequency, and uses EDA development tool QUARTUS ⅱ 3.0 to program CPLD, reapzes main logic function such as counter;
同时在该原理基础上,采用了Veriloghdl语言设计了高速的等精度测频模块,并且利用EDA开发平台QUARTUSⅡ3.0对CPLD芯片进行写入,实现了计数等主要逻辑功能;
With the rapid increase of signal frequency and decrease of feature sizes in high speed integrated circuit ( IC ) systems, interconnects play increasingly important roles, and the analysis of the time-domain response of interconnects becomes necessary to ensure the circuit designed working properly.
在高速集成电路(HSIC)系统当中,随着信号频率的增加和特征尺寸的减小,互连线的作用显得越来越重要,互连线的时域响应分析成了保证所设计的电路能正常工作的必要环节。
Based on the trade-off of the data decompression difficulty, a method of test data compression using the Golomb algorithm is provided for the portable test equipment. Then the corresponding decompression circuit is designed with the VHDL ( very high speed integrated circuit hardware description language ).
基于解压缩实现难易程度的折衷考虑,提出了基于Golomb算法的便携式检测设备的测试向量压缩方法,采用VHDL方法设计了相应的硬件解压缩电路,并且将其应用于便携式飞参检测设备。
上述内容是“High Speed Integrated Circuit”作为“HSIC”的缩写,解释为“高速集成电路”时的信息,以及英语缩略词HSIC所代表的英文单词,其对应的中文拼音、详细解释以及在英语中的流行度和相关分类、应用领域及应用示例等。
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